Power amplifier and communication apparatus

ABSTRACT

A power amplifier of amplifying signals of two frequency bands is reduced in size and improved in efficiency at low output.  
     The power amplifier includes an input terminal, a branch circuit and so on having one input and a plurality of outputs, the input being connected to the input terminal, amplifying means which are connected to some outputs of the branch circuit and so on and are operated at different signal frequencies from each other, a transmission line connected to one of the other outputs of the branch circuit, a synthesizing circuit connected to the outputs of the amplifying means and the output from the transmission line, a switch provided between the transmission line and a synthesis output unit, and a control circuit of controlling conduction of the branch circuit and so on, conduction and an amplifying operation of the amplifying means, and conduction of the switch.

TECHNICAL FIELD

[0001] The present invention mainly relates to a power amplifier and acommunication apparatus that are used for mobile communication and soon.

BACKGROUND ART

[0002] Applications with a variety of methods and frequency bands arepresent in mobile communication, and it has been desirable to handle aplurality of applications in radios. Some applications, typified byCDMA, require control on output power of radios and lower powerconsumption has been demanded over a wide dynamic range. Further,smaller radios reduced in weight have been also demanded.

[0003] Hereinafter, a conventional power amplifier will be discussedbelow in accordance with accompanying drawings.

[0004]FIG. 7 is a block diagram showing a conventional power amplifier700. In FIG. 7, reference numeral 701 denotes a first input terminal,reference numeral 702 denotes a first input-side matching circuit,reference numeral 703 denotes a first input-side DC bias supply circuit,reference numeral 704 denotes a first transistor, reference numeral 705denotes a first output-side DC bias supply circuit, reference numeral706 denotes a first output-side matching circuit, reference numeral 707denotes a first output terminal, reference numeral 708 denotes a secondinput terminal, reference numeral 709 denotes a second input-sidematching circuit, reference numeral 710 denotes a second input-side DCbias supply circuit, reference numeral 711 denotes a second transistor,reference numeral 712 denotes a second output-side DC bias supplycircuit, reference numeral 713 denotes a second output-side matchingcircuit, and reference numeral 714 denotes a second output terminal.

[0005] The conventional power amplifier configured thus performs anoperation on signals of two kinds of frequencies. The operation isperformed as follows: in the case of an operation at a first frequency,a signal inputted to the first input terminal 702 is amplified by thefirst transistor 704 and is outputted to the first output terminal 707.In the case of an operation at a second frequency, a signal inputted tothe second input terminal 708 is amplified by the second transistor 712and is outputted to the second output terminal 714.

[0006] Moreover, for the signal inputs of the two kinds of frequencies,even when a signal with low output is obtained, the signal is passedthrough the first transistor 704 or the second transistor 712 and anamplifying operation is performed.

[0007] However, in such a configuration, there is a problem that thepower amplifier is completely independent at each of the frequencies,and the number of components (not shown) between the power amplifier andan antenna is required for two systems, resulting in a large radio.

[0008] Furthermore, there is another problem that in use for amultistage amplifier and so on, since a power amplifier is generallyadjusted so as to have the highest efficiency at the maximum output,even when output is reduced and a signal of low power is necessary, thepower amplifier is operated. Thus, efficiency is overall degraded.

DISCLOSURE OF THE INVENTION

[0009] The present invention is devised to solve the above problems andhas as its object the provision of a power amplifier having one systemof input and output operating at a plurality of different frequencies,and a power amplifier which switches signal paths according to outputpower and achieves low power consumption even at low output.

[0010] To achieve the above object, a first invention of the presentinvention (corresponding to claim 1) is a power amplifier, comprising:

[0011] branch output means having an input terminal and a plurality ofoutput terminals,

[0012] a plurality of amplifying means which are connected to some ofthe output terminals of the branch output means and are operated atdifferent signal frequencies from each other,

[0013] bypass means connected to the other output terminals of thebranch output means,

[0014] a synthesis output unit which receives outputs of the pluralityof amplifying means and an output from the bypass means as inputs andhas an output terminal connected to an outside,

[0015] switch means of switching presence and absence of conduction ofthe bypass means, and

[0016] control means of controlling conduction of the branch outputmeans, conduction and an amplifying operation of the plurality ofamplifying means, and conduction of the switch means,

[0017] wherein according to the signal frequency and necessary outputpower, the control means performs control so that an input to the branchoutput means is amplified and outputted to the synthesis output unit viaany one of the plurality of amplifying means or the input is outputtedto the synthesis output unit via the bypass means without amplification.

[0018] A second invention of the present invention (corresponding toclaim 2) is a power amplifier, comprising:

[0019] branch output means having an input terminal and a plurality ofoutput terminals,

[0020] a plurality of amplifying means which are connected to some ofoutputs of the branch output means and are operated at different signalfrequencies from each other,

[0021] a bypass transmission line group which is connected to the otheroutput terminals of the branch output means and has a plurality ofbypass transmission lines connected in series with each other,

[0022] a synthesis output unit connected to each output of the pluralityof amplifying means and an output from the transmission line group,

[0023] first grounding means which is provided on a first node of thetransmission line group and the branch output means and permits controlof conduction,

[0024] a plurality of second grounding means which are provided onsecond nodes between the bypass transmission lines of the transmissionline group and permit control of conduction, and

[0025] control means of controlling conduction of the branch outputmeans, conduction and an amplifying operation of the plurality ofamplifying means, conduction of the first grounding means, andconduction of the second grounding means,

[0026] wherein taken from the synthesis output unit, a partial lengthfrom the transmission line group to each of the second nodes and anoverall length of the transmission line group correspond to each of thesignal frequencies of the plurality of amplifying means,

[0027] the partial lengths starting with the shortest one sequentiallycorrespond to the signal frequencies of the plurality of amplifyingmeans, starting from the highest frequency to the lowest frequency,

[0028] the overall length corresponds to the lowest signal frequency ofthe plurality of amplifying means, and

[0029] according to the signal frequency and necessary output power, thecontrol means performs control so that an input to the branch outputmeans is amplified and outputted to the synthesis output unit via anyone of the plurality of amplifying means or the input is outputted tothe synthesis output unit via the transmission line group withoutamplification.

[0030] A third invention of the present invention (corresponding toclaim 3) is a power amplifier, comprising:

[0031] branch output means having an input terminal and a plurality ofoutput terminals,

[0032] a plurality of amplifying means which are connected to some ofoutputs of the branch output means and are operated at different signalfrequencies from each other,

[0033] a transmission line connected to the other outputs of the branchoutput means,

[0034] a synthesis output unit connected to each output of the pluralityof amplifying means and an output from the transmission line,

[0035] grounding means which is provided on a side of the branch outputmeans of the transmission line and permits control of conduction, and

[0036] control means of controlling conduction of the branch outputmeans, conduction and an amplifying operation of the plurality ofamplifying means, and conduction of the grounding means,

[0037] wherein the signal frequencies are different from one another byeven number times,

[0038] a line length of the transmission line is one fourth of awavelength of a signal of which the signal frequency is the lowest, and

[0039] outputted to the synthesis output unit via any one of theplurality of amplifying means or the input is outputted to the synthesisoutput unit via the transmission line without amplification.

[0040] A fourth invention of the present invention (corresponding toclaim 4) is the power amplifier according to any one of the first to thethird inventions of the present invention, wherein the amplifying meanscomprises:

[0041] a first matching circuit provided on a side of the branch inputmeans,

[0042] a second matching circuit provided on a side of the synthesisoutput unit,

[0043] a transistor provided between the first matching circuit and thesecond matching circuit, and

[0044] a DC bias supply circuit provided between the first matchingcircuit and the transistor and/or between the second matching circuitand the transistor;

[0045] and at least one of the first matching circuit and the secondmatching circuit has variable impedance.

[0046] A fifth invention of the present invention (corresponding toclaim 5) is the power amplifier according to the fourth invention of thepresent invention, wherein the control means changes impedance of one orboth of the first matching circuit and the second matching circuitaccording to output of any one of the plurality of operated amplifyingmeans, the matching circuits being held by the operated amplifyingmeans.

[0047] A sixth invention of the present invention (corresponding toclaim 6) is the power amplifier according to the fourth invention of thepresent invention, wherein the first matching circuit and/or the secondmatching circuit comprises:

[0048] an input terminal connected to the branch input means or anoutput side of the transistor,

[0049] an output terminal connected to an input side of the transistoror the synthesis output unit,

[0050] at least one series matching circuit element connected betweenthe input terminal and the output terminal,

[0051] at least one switch which is connected between the input terminaland the series matching circuit element, between the two series matchingcircuit elements, or between the series matching circuit element and theoutput terminal, and is controlled to as to be turned on and off by thecontrol means, and

[0052] a parallel matching circuit element connected to the other end ofthe switch.

[0053] A seventh invention of the present invention (corresponding toclaim 7) is the power amplifier according to any one of the first to thethird inventions of the present invention, wherein the branch inputmeans comprises:

[0054] an amplifying means input switch for conduction with each of theplurality of amplifying means, and

[0055] a bypass input switch for conduction with one of the bypassmeans, the transmission line, and the transmission line group;

[0056] and the amplifying means input switch operates as a distortionpre-compensating circuit.

[0057] An eighth invention of the present invention (corresponding toclaim 8) is the power amplifier according to the seventh invention ofthe present invention, wherein the amplifying means input switch has adiode controlled so as to be turned on and off by input-side DC bias tothe amplifying means.

[0058] A ninth invention of the present invention (corresponding toclaim 9) is the power amplifier according to the fourth invention of thepresent invention, further comprising a DC bias supply circuit for multifrequencies connected to a node between the output synthesis unit andthe output terminal,

[0059] wherein the DC bias supply circuit for multi frequencies operatesaccording to the signal frequency corresponding to the operatingamplifying means of the plurality of amplifying means.

[0060] A tenth invention of the present invention (corresponding toclaim 10) is the power amplifier according to the ninth invention of thepresent invention, wherein the DC bias supply circuit for multifrequencies comprises:

[0061] a transmission line group having a plurality of bias transmissionlines which correspond to signal frequencies corresponding to theplurality of amplifying means and are connected in series with eachother,

[0062] a first bypass capacitor which is connected to one end of ahighest-frequency bias transmission line corresponding to the highestsignal frequency, which is provided on one end of the transmission linegroup and has the other end connected to the node,

[0063] a first sub switch which is connected in series with the firstbypass capacitor and is controlled so as to be turned on and off by thecontrol means,

[0064] at least one second bypass capacitor connected between theplurality of bias transmission lines of the transmission line group,

[0065] a second sub switch connected in series with the second bypasscapacitor, and

[0066] a bias terminal which is provided on the other end of thetransmission line group, is connected to a side not being connected tothe other bias transmission lines, and is fed with DC bias supplied fromthe control means;

[0067] and the other end of the highest-frequency bias transmission lineis grounded via the first bypass capacitor and the first sub switch,

[0068] grounding is made between the plurality of bias transmissionlines of the transmission line group other than the other end of thehighest-frequency bias transmission line via the second bypass capacitorand the second sub switch,

[0069] the first bypass capacitor is short-circuited at the highestsignal frequency of the signal frequencies, and

[0070] the second bypass capacitor is short-circuited at the signalfrequency associated with a sum of lengths of transmission lines fromthe connecting position to the node.

[0071] An eleventh invention of the present invention (corresponding toclaim 11) is a power amplifier having a multistage constitution, whereinthe power amplifier described in any one of the first to the tenthinventions of the present invention is combined and used as an amplifierof at least one stage or more.

[0072] A twelfth invention of the present invention (corresponding toclaim 12) is a power amplifier, wherein all or some parts of the poweramplifier described in any one of the first to the tenth inventions ofthe present invention are configured on the same semiconductorsubstrate.

[0073] A thirteenth invention of the present invention (corresponding toclaim 13) is a power amplifier, wherein all or some parts of the poweramplifier described in any one of the first to the tenth inventions ofthe present invention are configured on a plurality of differentsemiconductor substrates from each other.

[0074] A fourteenth invention of the present invention (corresponding toclaim 14) is a communication apparatus, comprising:

[0075] a signal processing circuit,

[0076] a transmitting circuit which transmits a signal from the signalprocessing circuit and has a power amplifier,

[0077] an antenna which transmits an output of the transmitting circuitand receives a reception signal, and

[0078] a receiving circuit of processing the reception signal,

[0079] wherein the power amplifier is the power amplifier described inany one of the first to the thirteenth inventions of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0080]FIG. 1 is a block diagram showing the configuration according toEmbodiment 1 of the present invention;

[0081]FIG. 2 is a block diagram showing the configuration according toEmbodiment 2 of the present invention;

[0082]FIG. 3 is a block diagram showing the configuration of a matchingcircuit according to Embodiments 1 to 3 of the present invention;

[0083]FIG. 4 is a block diagram showing an input changeover switchaccording to Embodiment 4 of the present invention;

[0084]FIG. 5 is a block diagram showing the configuration according toEmbodiment 5 of the present invention;

[0085]FIG. 6 is a block diagram showing one example of a mobile wirelessunit according to the present invention;

[0086]FIG. 7 is a block diagram showing the configuration of aconventional power amplifier;

[0087]FIG. 8 is a partial structural diagram for explaining the casewhere the input changeover switch of Embodiment 4 is used for Embodiment1 according to the present invention; and

[0088]FIG. 9 is a block diagram showing the configuration according toEmbodiment 3 of the present invention.

DESCRIPTION OF THE SYMBOLS

[0089]100, 200, 500, 603 power amplifier

[0090]101, 201, 301, 401, 501, 701, 708 input terminal

[0091]102, 202, 502 branch circuit

[0092]103, 105, 107, 109, 203, 205, 207, 209, 302, 305, 503,

[0093]505, 507, 509 switch

[0094]104, 106, 204, 206, 504, 506 amplifying means

[0095]104 a, 104 b, 106 a, 106 b, 204 a, 204 b, 206 a, 206 b, 300, 504a,

[0096]504 b, 506 a, 506 b, 702, 706, 709, 713 matching circuit

[0097]104 c, 104 d, 106 c, 106 d, 204 c, 204 d, 206 c, 206 d, 504 c,

[0098]506 c, 703, 705, 710, 711 DC bias supply circuit

[0099]104 c, 106 c, 204 c, 206 c, 504 d, 506 d, 704, 712 transistor

[0100]108, 208, 508, 512 a, 512 d transmission line

[0101]110, 210, 510 synthesizing circuit

[0102]111, 211, 307, 404, 511, 707, 714 output terminal

[0103]112, 212, 513 control circuit

[0104]303, 306 parallel matching circuit element

[0105]304 series matching circuit element

[0106]402 DC AC separation circuit

[0107]402 a AC signal path

[0108]402 b DC signal path

[0109]403 diode

[0110]512 c, 512 f sub switch

[0111]512 b, 512 e bypass capacitor

[0112]512 g DC bias supply terminal

[0113]514 node

[0114]600 portable radio

[0115]601 signal processing section

[0116]602 transmitting circuit

[0117]604 antenna

[0118]605 receiving circuit

MODE FOR CARRYING OUT THE INVENTION

[0119] Referring to the accompanying drawings, the following willdescribe operation of a power amplifier according to embodiments of thepresent invention.

[0120] (Embodiment 1)

[0121] Referring to FIG. 1, Embodiment 1 of the present invention willbe discussed below. FIG. 1 is a block diagram showing a power amplifier100 according to Embodiment 1 of the present invention. In FIG. 1,reference numeral 101 denotes an input terminal, reference numeral 102denotes a branch circuit, reference numeral 103 denotes a first switch,reference numeral 104 denotes first amplifying means operating at afirst frequency, reference numeral 104 a denotes an input-side matchingcircuit, reference numeral 104 b denotes an output-side matchingcircuit, reference numeral 104 c denotes an input-side DC bias supplycircuit, reference numeral 104 d denotes an output-side DC bias supplycircuit, reference numeral 104 e denotes a transistor, reference numeral105 denotes a second switch, reference numeral 106 denotes secondamplifying means operating at a second frequency, reference numeral 106a denotes an input-side matching circuit, reference numeral 106 bdenotes an output-side matching circuit, reference numeral 106 c denotesan input-side DC bias supply circuit, reference numeral 106 d denotes anoutput-side DC bias supply circuit, reference numeral 106 e denotes atransistor, reference numeral 107 denotes a third switch, referencenumeral 108 denotes a transmission line, reference numeral 109 denotes afourth switch, reference numeral 110 denotes a synthesizing circuit,reference numeral 111 denotes an output terminal, and reference numeral112 denotes a control circuit.

[0122] The power amplifier 100 configured thus according to the presentembodiment performs the operation described below.

[0123] The power amplifier 100 operates at the first frequency. In afirst mode requiring an amplifying operation, the first switch 103 isturned on and the second to fourth switches 105, 107, and 109 are turnedoff by the control circuit 112. DC bias is supplied to the transistor104 e of the first amplifying means 104 via the DC bias supply circuits104 c and 104 d so that a desired initial current is obtained. DC biasis supplied to the transistor 106 e of the second amplifying means 106via the DC bias supply circuits 106 c and 106 d so that an amplifyingoperation is not performed.

[0124] At this point, at the first frequency, the input-side andoutput-side matching circuits 106 a and 106 b of the second amplifyingmeans 106 are changed by the control circuit 112 so that impedance tothe second amplifying means 106 from an input connected to the secondamplifying means 106 of the synthesizing circuit 110 is high impedance.However, only the output-side matching circuit 106 b may be changed andthe input-side matching circuit 106 a does not always have to bechanged.

[0125] Thus, a signal inputted from the input terminal 101 is amplifiedby the first amplifying means 104, and its output signal is outputtedfrom the output terminal 111.

[0126] In a second mode operating at the first frequency and requiringno amplifying operation, the first and second switches 103 and 105 areturned off and the third and fourth switches 107 and 109 are turned onby the control circuit 112. DC bias is supplied to the transistors 104 eand 106 e of the first and second amplifying means 104 and 106 via theDC bias supply circuits 104 c, 104 d, 106 c, and 106 d so that anamplifying operation is not performed.

[0127] At this point, at the first frequency, the input-side andoutput-side matching circuits 104 a and 104 b of the first amplifyingmeans 104 are changed by the control circuit 112 so that impedance tothe first amplifying means 104 from an input connected to the firstamplifying means 104 of the synthesizing circuit 110 is high impedance.The input-side and output-side matching circuits 106 a and 106 b of thesecond amplifying means 106 are changed by the control circuit 112 sothat impedance to the second amplifying means 106 from the inputconnected to the second amplifying means 106 of the synthesizing circuit110 is high impedance. However, only the output-side matching circuit106 b may be changed and the input-side matching circuit 106 a does notalways have to be changed.

[0128] Hence, a signal inputted from the input terminal 101 passesthrough the transmission line 108 and its output signal is outputtedfrom the output terminal 111.

[0129] In a third mode operating at the second frequency and requiringan amplifying operation, the second switch 105 is turned on and thefirst, third and fourth switches 103, 107, and 109 are turned off by thecontrol circuit 112. DC bias is supplied to the transistor 106 e of thesecond amplifying means 106 via the DC bias supply circuits 106 c and106 d so that a desired initial current is obtained. DC bias is suppliedto the transistor 104 e of the first amplifying means 104 via the DCbias supply circuits 104 c and 104 d so that an amplifying operation isnot performed.

[0130] At this point, at the second frequency, the input-side andoutput-side matching circuits 104 a and 104 b of the first amplifyingmeans 104 are changed by the control circuit 112 so that impedance tothe first amplifying means 104 from the input connected to the firstamplifying means 104 of the synthesizing circuit 110 is high impedance.However, only the output-side matching circuit 104 b may be changed andthe input-side matching circuit 104 a does not always have to bechanged.

[0131] Hence, a signal inputted from the input terminal 101 is amplifiedby the second amplifying means 106, and its output signal is outputtedfrom the output terminal 111.

[0132] In a fourth mode operating at the second frequency and requiringno amplifying operation, the first and second switches 103 and 105 areturned off and the third and fourth switches 107 and 109 are turned onby the control circuit 112. DC bias is supplied to the transistors 104 eand 106 e of the first and second amplifying means 104 and 106 via theDC bias supply circuits 104 c, 104 d, 106 c, and 106 d so that anamplifying operation is not performed.

[0133] At this point, at the second frequency, the input-side andoutput-side matching circuits 104 a and 104 b of the first amplifyingmeans 104 are changed by the control circuit 112 so that impedance tothe first amplifying means 104 from the input connected to the firstamplifying means 104 of the synthesizing circuit 110 is high impedance,and the input-side and output-side matching circuits 106 a and 106 b ofthe second amplifying means 106 are changed by the control circuit 112so that impedance to the second amplifying means 106 from the inputconnected to the second amplifying means 106 of the synthesizing circuit110 is high impedance. However, only the output-side matching circuits104 b and 106 b may be changed and the input-side matching circuits 104a and 106 a do not always have to be changed.

[0134] Hence, a signal inputted from the input terminal 101 passesthrough the transmission line 108 and its output signal is outputtedfrom the output terminal 111.

[0135] The control circuit 112 performs control to switch the above fourmodes according to an operating frequency and output power.

[0136] As described above, according to the present embodiment, signalpaths are switched according to an operating frequency and output power.Particularly in the second and fourth modes, an output signal is causedto bypass from the amplifying means and bias voltage not operating theamplifying means is supplied, so that consumed current of the amplifierfor lower output power is reduced, thereby improving efficiency in awide output range. Further, a signal path not requiring an amplifyingoperation is shared at two frequencies, and the output of the amplifieris provided as a single system, thereby reducing the size of thecircuit.

[0137] Besides, the above explanation describes that the power amplifier100 comprises the two amplifying means of the first amplifying means 104which amplifies a signal of the first frequency and the secondamplifying means 106 which amplifies a signal of the second frequency.The power amplifier of the present invention is not limited to theabove. Three or more amplifying means may be provided for amplifyingsignals of different frequencies. In this case, a signal path notrequiring amplifying operation can be shared at three frequencies ormore.

[0138] (Embodiment 2)

[0139] Referring to FIG. 2, Embodiment 2 of the present invention willbe discussed below. FIG. 2 is a block diagram showing a power amplifier200 according to Embodiment 2 of the present invention. In FIG. 2,reference numeral 201 denotes an input terminal, reference numeral 202denotes a branch circuit, reference numeral 203 denotes a first switch,reference numeral 204 denotes first amplifying means operating at afirst frequency, reference numeral 204 a denotes an input-side matchingcircuit, reference numeral 204 b denotes an output-side matchingcircuit, reference numeral 204 c denotes an input-side DC bias supplycircuit, reference numeral 204 d denotes an output-side DC bias supplycircuit, reference numeral 204 e denotes a transistor, reference numeral205 denotes a second switch, reference numeral 206 denotes secondamplifying means operating at a second frequency which is even numbertimes larger than the first frequency, reference numeral 206 a denotesan input-side matching circuit, reference numeral 206 b denotes anoutput-side matching circuit, reference numeral 206 c denotes aninput-side DC bias supply circuit, reference numeral 206 d denotes anoutput-side DC bias supply circuit, reference numeral 206 e denotes atransistor, reference numeral 207 denotes a third switch, referencenumeral 208 denotes a transmission line, reference numeral 209 denotes afourth switch, reference numeral 210 denotes a synthesizing circuit,reference numeral 211 denotes an output terminal, and reference numeral212 denotes a control circuit.

[0140] Here, it is desirable that a line length of the transmission line208 be one fourth of a wavelength of a first-frequency signal.

[0141] The power amplifier 200 configured thus according to the presentembodiment performs the operation described below.

[0142] The power amplifier 200 operates at the first frequency. In afirst mode requiring an amplifying operation, the first and fourthswitches 203 and 209 are turned on and the second and third switches 205and 207 are turned off by the control circuit 212. DC bias is suppliedto the transistor 204 e of the first amplifying means 204 via the DCbias supply circuits 204 c and 204 d so that a desired initial currentis obtained. DC bias is supplied to the transistor 206 e of the secondamplifying means 206 via the DC bias supply circuits 206 c and 206 d sothat an amplifying operation is not performed.

[0143] At this point, at the first frequency, the input-side andoutput-side matching circuits 206 a and 206 b of the second amplifyingmeans 206 are changed by the control circuit 212 so that impedance tothe second amplifying means 206 from an input connected to the secondamplifying means 206 of the synthesizing circuit 210 is high impedance.However, only the output-side matching circuit 206 b may be changed andthe input-side matching circuit 206 a does not always have to bechanged.

[0144] Further, since the fourth switch 209 is turned on, impedance tothe transmission line 208 from an input connected to the transmissionline 208 of the synthesizing circuit 210 is high impedance at the firstfrequency and low impedance at the second frequency.

[0145] Hence, a signal inputted from the input terminal 201 is amplifiedby the first amplifying means 204, and its output signal is outputtedfrom the output terminal 211.

[0146] In a second mode operating at the first frequency and requiringno amplifying operation, the first, second, and fourth switches 203,205, and 209 are turned off and the third switch 207 is turned on by thecontrol circuit 212. DC bias is supplied to the transistors 204 e and206 e of the first and second amplifying means 204 and 206 via the DCbias supply circuits 204 c, 204 d, 206 c, and 206 d so that anamplifying operation is not performed.

[0147] At this point, at the first frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means 204 from an input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance.The input-side and output-side matching circuits 206 a and 206 b of thesecond amplifying means 206 are changed by the control circuit 112 sothat impedance to the second amplifying means 206 from the inputconnected to the second amplifying means 206 of the synthesizing circuit210 is high impedance. However, only the output-side matching circuits204 b and 206 b may be changed and the input-side matching circuits 204b and 206 a do not always have to be changed.

[0148] Hence, a signal inputted from the input terminal 201 passesthrough the transmission line 208, and its output signal is outputtedfrom the output terminal 211.

[0149] In a third mode operating at the second frequency and requiringan amplifying operation, the second switch 205 is turned on and thefirst, third and fourth switches 203, 207, and 209 are turned off by thecontrol circuit 212. DC bias is supplied to the transistor 206 e of thesecond amplifying means 206 via the DC bias supply circuits 206 c and206 d so that a desired initial current is obtained. DC bias is suppliedto the transistor 204 e of the first amplifying means 204 via the DCbias supply circuits 204 c and 204 d so that an amplifying operation isnot performed.

[0150] At this point, at the second frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means 204 from the input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance.However, only the output-side matching circuit 204 b may be changed andthe input-side matching circuit 204 a does not always have to bechanged.

[0151] Further, since the third and fourth switches 207 and 209 areturned off, impedance to the transmission line 208 from the inputconnected to the transmission line 208 of the synthesizing circuit 210is high impedance at the second frequency.

[0152] Hence, a signal inputted from the input terminal 201 is amplifiedby the second amplifying means 206, and its output signal is outputtedfrom the output terminal 211.

[0153] In a fourth mode operating at the second frequency and requiringno amplifying operation, the first, second, and fourth switches 203,205, and 209 are turned off and the third switch 207 is turned on by thecontrol circuit 212. DC bias is supplied to the transistors 204 e and206 e of the first and second amplifying means 204 and 206 via the DCbias supply circuits 204 c, 204 d, 206 c, and 206 d so that anamplifying operation is not performed.

[0154] At this point, at the second frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means 204 from the input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance,and the input-side and output-side matching circuits 206 a and 206 b ofthe second amplifying means 206 are changed by the control circuit 212so that impedance to the second amplifying means 206 from the inputconnected to the second amplifying means 206 of the synthesizing circuit210 is high impedance. However, only the output-side matching circuits204 b and 206 b may be changed and the input-side matching circuits 204a and 206 a do not always have to be changed.

[0155] Hence, a signal inputted from the input terminal 201 passesthrough the transmission line 208 and its output signal is outputtedfrom the output terminal 211.

[0156] The control circuit 212 performs control to switch the above fourmodes, first to fourth modes according to an operating frequency andoutput power.

[0157] As described above, according to the present embodiment, in thecase where one operating frequency is even number times larger than theother operating frequency, even when the circuit configuration ischanged, it is possible to perform the same operation as Embodiment 1.Moreover, when the amplifying means is operated at a low frequency, thetransmission line 208 has low impedance at a high frequency which is aharmonic of an output signal of a low frequency and suppresses aharmonic content. Thus, it is possible to realize a higher harmonicprocessing circuit without the necessity for providing another circuitfor harmonic processing.

[0158] Further, as compared with Embodiment 1, since no switch isprovided between the transmission line 208 and the synthesizing circuit210, it is possible to reduce internal loss and efficiently transmitsignals.

[0159] Besides, the above explanation has described that the poweramplifier 200 comprises the two amplifying means of the first amplifyingmeans 204 which amplifies a signal of the first frequency and the secondamplifying means 206 which amplifies a signal of the second frequencywhich is even number times larger than the first frequency. The poweramplifier of the present invention is not limited to the above. Three ormore amplifying means may be provided for amplifying signals whosefrequencies are different from one another by even number times.

[0160] (Embodiment 3)

[0161] Referring to FIG. 9, Embodiment 3 of the present invention willbe discussed below. FIG. 9 is a block diagram showing a power amplifier900 according to Embodiment 3 of the present invention. In FIG. 9, thesame parts or the corresponding parts of FIG. 2 are indicated by thesame reference numerals and the detailed description thereof will beomitted. However, as to the relationship between a first frequency wherefirst amplifying means 204 operates and a second frequency where secondamplifying means 206 operates, the second frequency is simply set higherthan the first frequency and does not have to be higher than the firstfrequency by even number times.

[0162] Further, reference numeral 230 denotes a first transmission lineand reference numeral 231 denotes a second transmission line. The firsttransmission line 230 and the second transmission line 231 have each oneend connected in series with each other via the second node 234 b. Theother end of the first transmission line 230 is connected to a firstnode 234 a between a third switch 207 and a fourth switch 209 and theother end of the second transmission line 231 is connected to asynthesizing circuit 210, so that a bypass transmission line group ofthe present invention is formed. Moreover, a fifth switch 232 whereconduction is controlled by control means 212 is provided on the secondnode 234 b, and the second node 234 b is grounded via the fifth switch232.

[0163] Here, the second transmission line 231 has a line length which isone fourth of a wavelength of a second frequency signal on the side ofthe second amplifying means 206, and the sum of the line length of thefirst transmission line 230 and the line length of the secondtransmission line 231 is one fourth of a wavelength of a first frequencysignal on the side of the first amplifying means 204.

[0164] The power amplifier 900 configured thus according to the presentembodiment performs the operation described below.

[0165] The power amplifier 900 operates at the first frequency. In afirst mode requiring an amplifying operation, first and fourth switches203 and 209 are turned on and the second, third, and fifth switches 205,207, and 232 are turned off by the control circuit 212. DC bias issupplied to a transistor 204 e of the first amplifying means 204 via DCbias supply circuits 204 c and 204 d so that a desired initial currentis obtained. DC bias is supplied to a transistor 206 e of the secondamplifying means 206 via DC bias supply circuits 206 c and 206 d so thatan amplifying operation is not performed.

[0166] At this point, at the first frequency, input-side and output-sidematching circuits 206 a and 206 b of the second amplifying means 206 arechanged by the control circuit 212 so that impedance to the secondamplifying means 206 from an input connected to the second amplifyingmeans 206 of the synthesizing circuit 210 is high impedance. However,only the output-side matching circuit 206 b may be changed and theinput-side matching circuit 206 a does not always have to be changed.

[0167] Further, since the fourth switch 209 is turned on and the fifthswitch 232 is turned off, impedance to the first transmission line 230and the second transmission line 231 from an input connected to thefirst transmission line 230 and the second transmission line 231 of thesynthesizing circuit 210 is high impedance at the first frequency.

[0168] Hence, a signal inputted from the input terminal 201 is amplifiedin the first amplifying means 204 and its output signal is outputtedfrom the output terminal 211.

[0169] In a second mode operating at the first frequency and requiringno amplifying operation, the first, second, fourth, and fifth switches203, 205, 209, and 232 are turned off and the third switch 207 is turnedon by the control circuit 112. DC bias is supplied to the transistors204 e and 206 e of the first and second amplifying means 204 and 206 viathe DC bias supply circuits 204 c, 204 d, 206 c, and 206 d so that anamplifying operation is not performed.

[0170] At this point, at the first frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means 204 from an input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance,and the input-side and output-side matching circuits 206 a and 206 b ofthe second amplifying means 206 are changed by the control circuit 212so that impedance to the second amplifying means 206 from the inputconnected to the second amplifying means 206 of the synthesizing circuit210 is high impedance. However, only the output-side matching circuits204 b and 206 b may be changed and the input-side matching circuits 204b and 206 a do not always have to be changed.

[0171] Hence, a signal inputted from the input terminal 201 passesthrough the first transmission line 230 and the second transmission line231 and its output signal is outputted from an output terminal 211.

[0172] In a third mode operating at a second frequency and requiring anamplifying operation, the second switch 205 and the fifth switch 232 areturned on and the first, third and fourth switches 203, 207, and 209 areturned off by the control circuit 212. DC bias is supplied to thetransistor 206 e of the second amplifying means 206 via the DC biassupply circuits 206 c and 206 d so that a desired initial current isobtained. DC bias is supplied to the transistor 204 e of the firstamplifying means 204 via the DC bias supply circuits 204 c and 204 d sothat an amplifying operation is not performed.

[0173] At this point, at the second frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means. 204 from the input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance.However, only the output-side matching circuit 204 b may be changed andthe input-side matching circuit 204 a does not always have to bechanged.

[0174] Further, since the third and fourth switches 207 and 209 areturned off and the fifth switch 232 is turned on, impedance to thesecond transmission line 231 from an input connected to the secondtransmission line 231 of the synthesizing circuit 210 is high impedanceat the second frequency.

[0175] Hence, a signal inputted from the input terminal 201 is amplifiedin the second amplifying means 206 and its output signal is outputtedfrom the output terminal 211.

[0176] In a fourth mode operating at the second frequency and requiringno amplifying operation, the first, second, fourth, and fifth switches203, 205, 209, and 232 are turned off and the third switch 207 is turnedon by the control circuit 212. DC bias is supplied to the transistors204 e and 206 e of the first and second amplifying means 204 and 206 viathe DC bias supply circuits 204 c, 204 d, 206 c, and 206 d so that anamplifying operation is not performed.

[0177] At this point, at the second frequency, the input-side andoutput-side matching circuits 204 a and 204 b of the first amplifyingmeans 204 are changed by the control circuit 212 so that impedance tothe first amplifying means 204 from the input connected to the firstamplifying means 204 of the synthesizing circuit 210 is high impedance,and the input-side and output-side matching circuits 206 a and 206 b ofthe second amplifying means 206 are changed by the control circuit 212so that impedance to the second amplifying means 206 from the inputconnected to the second amplifying means 206 of the synthesizing circuit210 is high impedance. However, only the output-side matching circuits204 b and 206 b may be changed and the input-side matching circuits 204a and 206 a do not always have to be changed.

[0178] Hence, a signal inputted from the input terminal 201 passesthrough the first transmission line 230 and the second transmission line231 and its output signal is outputted from the output terminal 211.

[0179] The control circuit 212 performs control to switch the above fourmodes, the first to fourth modes according to an operating frequency andoutput power.

[0180] As described above, according to the present embodiment, likeEmbodiment 1, an output signal is caused to bypass from the amplifyingmeans and bias voltage not operating the amplifying means is supplied,so that efficiency can be improved over a wide output range by reducingconsumed current of the amplifiers when output power is reduced.Further, when an amplifying operation is not necessary, the signal pathis shared at two frequencies and an output of the amplifier is providedas a single system, thereby achieving a smaller circuit. Since there isno switch between the first transmission line 230 and the secondtransmission line 231 and the synchronizing circuit 210, internal losscan be reduced accordingly and thus signals can be efficientlytransmitted.

[0181] Additionally, the above explanation has described that the poweramplifier 900 comprises the two amplifying means of the first amplifyingmeans 204 which amplifies a signal of the first frequency and the secondamplifying means 206 which amplifies a signal of the second frequencyhigher than the first frequency. The power amplifier of the presentinvention is not limited to the above. Three or more amplifying meansmay be provided for amplifying signals of different frequencies. At thispoint, the number of transmission lines connected in series is preparedaccording to the number of the amplifying means, and grounding is madebetween the transmission lines via a switch where conduction can becontrolled by control means, just like the fifth switch 232.

[0182] Taken from the synchronizing circuit 210, partial lengths of theplurality of transmission lines to the nodes and overall lengths of thetransmission lines connected in series are caused to correspond to thesignal frequencies of the plurality of amplifying means, respectively.It is preferable that the partial lengths starting with the shortest onesequentially correspond to signal frequencies of the plurality ofamplifying means, starting from the highest frequency to the lowestfrequency, and an overall length corresponding to the lowest signalfrequency of the plurality of amplifying means is used. The controlmeans controls conduction of the switches between the transmission linesaccording to frequencies of the operating amplifying means, so that thesame operation as that of the above embodiment can be performed evenwhen three or more amplifying means are provided. In this case as well,it is desirable that a length corresponding to a partial length and anoverall length be equivalent to one fourth of a wavelength correspondingto each of the signal frequencies.

[0183] Besides, in Embodiments 1 to 3, the first and second switches areoperated as distortion pre-compensating circuits, so that efficiency canbe improved particularly for a system demanding linearity.

[0184] Further, DC bias of the operating amplifying means can be changedaccording to output power to reduce consumed current is reduced whilesatisfying a desired characteristic, so that efficiency can be improved.

[0185] Furthermore, efficiency can be also improved by the followingoperation: one or both of the input-side and the output-side matchingcircuits of the operating amplifying means are changed according tooutput power and are used under an optimum load of the output power.

[0186]FIG. 3 is a block diagram showing one example of the configurationof the matching circuit in the amplifying means according to Embodiments1 to 3. In a matching circuit 300, reference-numeral 301 denotes aninput terminal, reference numeral 302 denotes a first switch, referencenumeral 303 denotes a first parallel matching circuit element, referencenumeral 304 denotes a series matching circuit element, reference numeral305 denotes a second switch, reference numeral 306 denotes a secondparallel matching circuit element, and reference numeral 307 denotes anoutput terminal. For example, the series matching circuit element isrealized by a coil, a capacitor, and a transmission line. For example,the element is realized as a coil having both ends respectivelyconnected to the input terminal 301 and the output terminal 307. Thefirst parallel matching circuit element 303 and the second parallelmatching circuit element 306 are realized as, for example, capacitorshaving one end being grounded.

[0187] The turning on and off of the first and second switches 302 and305 are switched in response to a control signal from the controlcircuits 112 and 212, so that the matching circuit 300 is changed inimpedance. The number of circuits composed of the first and secondswitches 302 and 305 and the first and second parallel matching circuitelements 303 and 306 is increased, so that the matching circuit can beadjusted in a more elaborate manner. When it is not necessary to switchthe matching circuits, a matching circuit with constant impedance can berealized by eliminating the circuit composed of the first and secondswitches 302 and 305 and the first and second parallel matching circuitelements 303 and 306. With the above arrangement, the operations ofEmbodiments 1 to 3 can be realized.

[0188] (Embodiment 4)

[0189]FIG. 4 is a block diagram showing an example in which theinput-side switches of amplifying means 104 and 106 (204 and 206) areeach constituted by a diode turned on and off by input-side DC bias of atransistor. FIG. 4 shows a circuit used when the input-side DC bias thatthe transistors of the amplifying means 104 and 106 require to performthe amplifying means needs positive voltage. A switch 400 is a switchused as the first switch 103 and the second switch 105 shown in FIG. 1.In the switch 400, reference numeral 401 denotes an input terminal,reference numeral 402 denotes a DC AC separation circuit, referencenumeral 402 a denotes an AC signal path, reference numeral 402 b denotesa DC signal path, reference numeral 403 denotes a diode, and referencenumeral 404 denotes an output terminal. Further, FIG. 8a shows a partialdiagram of a power amplifier when the switch 400 is used for the firstswitch 103 of Embodiment 1 (400 a in FIG. 8(a)) and when the switch 400is used for the second switch 105 of Embodiment 1 (400 b in FIG. 8(a)).Additionally, since the operations of the whole circuit are the same asthose of Embodiments 1 and 2, only the operations of the input-sideswitches of the first amplifying means 104 and the second amplifyingmeans 106 will be described later.

[0190] When the amplifying means 104 or 106 is operated, DC biassupplied to the input side of the transistor 104 e or 106 e is alsoapplied to the anode of the diode 403, and the cathode of the diode 403is grounded in DC manner by the DC AC separation circuit 402. Thus,current is applied to the diode 403 and the switch 400 is turned on.When the first amplifying means 104 or the second amplifying means 106is not operated, DC bias is supplied so that the transistor 104 e or 106e and the diode 403 are both turned off.

[0191] With this arrangement, the control terminals of the amplifyingmeans 104 and 106 and the input-side switches 103 and 105 can be sharedwhile realizing the operations of Embodiments 1 and 2, and control linesfrom the control circuit can be reduced.

[0192] Further, as shown in FIG. 8(b), the DC AC separation circuits 402respectively held by the switch 400 a serving as the first switch 103and the switch 400 b serving as the second switch 105 are shared. Andthe DC AC separation circuit 402 is arranged between the input terminal101 and a branch circuit 102, and the first and second switches arerealized respectively as 400 a′ and 400 b′, each being only composed ofthe diode 403. Thus, the circuit can be further reduced in size.

[0193] Moreover, it is apparent that improved efficiency of Embodiment 2can be achieved by operating the switch composed of the diode 403 as adistortion pre-compensating circuit.

[0194] (Embodiment 5)

[0195] Referring to FIG. 5, Embodiment 5 of the present invention willbe discussed below. FIG. 5 is a block diagram showing a power amplifier500 according to Embodiment 5 of the present invention. In FIG. 5, sincethe circuit configuration is almost the same as that of Embodiment 1,only different points will be described. First and second amplifyingmeans 504 and 506 are respectively composed of input-side matchingcircuits 504 a and 506 a, output-side matching circuits 504 b and 506 b,and transistors 504 d and 506 d having DC bias supply circuits 504 c and506 c only on the input side. Output-side DC bias of the transistors 504d and 506 d in the amplifying means 504 and 506 is supplied by a DC biassupply circuit for two frequencies 512. The DC bias supply circuit fortwo frequencies 512 is connected to a node 514 provided between asynthesizing circuit 510 and an output terminal 511. At this point, theoutput-side matching circuits 504 b and 506 b of the first and secondamplifying means both have to be configured so as to apply DC bias tothe transistors 504 d and 506 d. Besides, when necessary, a DC cutoffcircuit may be provided between the node 514 and the output terminal511.

[0196] In the DC bias supply circuit for two frequencies 512, a firstbias transmission line 512 a has one end directly connected between thesynthesizing circuit 510 and the output terminal 511 via the node 514and the other end connected to one end of a second bias transmissionline 512 d. The other end of the second bias transmission line 512 d isconnected to a DC bias supply terminal 512 g and fed with DC bias from acontrol circuit 513. Further, grounding is made between the first biastransmission line 512 a and the second bias transmission line 512 d viaa first bypass capacitor 512 b and a first sub switch 512 c, andgrounding is made between the second bias transmission line 512 d andthe DC bias supply terminal 512 g via a second bypass capacitor 512 eand a second sub switch 512 f. Further, the line length of the firstbias transmission line 512 a is one fourth of a wavelength of ahigh-frequency signal corresponding to the first amplifying means 504,and the sum of the line length of the first bias transmission line 512 aand the line length of the second bias transmission line 512 d is onefourth of a wavelength of a low frequency corresponding to the secondamplifying means 506.

[0197] The present embodiment configured thus is operated in thefollowing manner.

[0198] When an operation is performed at a high frequency of twofrequencies, the control circuit 513 performs control to turn on thefirst sub switch 512 c, and necessary DC bias is supplied to the DC biassupply terminal 512 g.

[0199] Hence, since grounding is made on the first bypass capacitor 512b connected to the first bias transmission line 512 a having a length ofone fourth of a wavelength at a high frequency, impedance to the DC biassupply circuit for two frequencies 512 from the node 514 at a highfrequency is high impedance.

[0200] When an operation is performed at a low frequency of twofrequencies, the control circuit 513 performs control to turn off thefirst sub switch 512 c and turn on the second sub switch 512 f, andnecessary DC bias is supplied to the DC bias supply terminal 512 g.

[0201] Hence, the sum of the lengths of the first and second biastransmission lines 512 a and 512 d is a length of one fourth of awavelength at a low frequency, and the second bypass capacitor 512 econnected to the second bias transmission line 512 d is grounded byturning on the second sub switch 512 f by the control circuit 513. Thus,impedance to the DC bias supply circuit for two frequencies 512 from thenode 514 at a low frequency is high impedance.

[0202] Hence, DC bias can be applied by the DC bias supply circuitshared by the two transistors without affecting a high-frequency signal.Additionally, even when the second sub switch 512 f (or a sub switchclosest to the DC bias supply terminal 152 g) is not present, the sameoperation can be performed and the number of switches requiring controlcan be reduced.

[0203] Although the above explanation has described the case with thecircuit configuration of Embodiment 1, the operation of Embodiment 2 canbe performed when the DC bias supply circuit for two frequencies is usedin the circuit configurations of Embodiments 2 and 3.

[0204] Although the above explanation has described that the first subswitch 512 c and the first sub switch 512 f are both provided betweenthe bypass capacitor and a ground, the capacitor and switches only haveto be connected in series and the bypass capacitor may be providedbetween the switches and the ground.

[0205] Besides, the above explanation has described that the poweramplifier 500 comprises the two amplifying means of the first amplifyingmeans 504 which amplifies a signal of a first frequency and the secondamplifying means 506 which amplifies a signal of a second frequency. Thepower amplifier of the present invention is not limited to the above.Like Embodiment 1, three or more amplifying means may be provided foramplifying signals of different frequencies. At this point, the DC biassupply circuit for two frequencies 512 serves as a DC bias supplycircuit for multi frequencies of dealing with signals as many as signalsprocessed by the amplifying means. And it is desirable that in the DCbias supply circuit for multi frequencies, as a highest-frequency biastransmission line of the present invention, one end of the biastransmission line having a one-fourth wavelength at the highestfrequency is connected to the node 514 and the number of biastransmission lines connected in series between the node 514 and the DCbias supply terminal 512 g is increased. At this point, it is desirablethat a length from the node 514 to the nodes of the increased biastransmission lines be set at one fourth of a wavelength of acorresponding signal of the amplifying means which corresponds to eachof the increased bias transmission lines.

[0206] Further, in the case of the configuration according to Embodiment2, three or more amplifying means may be provided for amplifying signalsof frequencies different from one another by even number times. In thiscase as well, the DC bias supply circuit for two frequencies 512 servesas a DC bias supply circuit for multi frequencies of dealing withsignals as many as signals processed by the amplifying means. And it isdesirable that in this DC bias supply circuit for multi frequencies, asa highest-frequency bias transmission line of the present invention, oneend of the bias transmission line having a one-fourth wavelength at thehighest frequency is connected to the node 514 and the number of biastransmission lines connected in series between the node 514 and the DCbias supply terminal 512 g is increased. At this point, it is desirablethat a length from the node 514 to the nodes of the increased biastransmission lines be set at one fourth of a wavelength of acorresponding signal of the amplifying means which corresponds to eachof the increased bias transmission lines.

[0207] Additionally, efficiency can be improved more elaborately in thestep of output power by connecting the power amplifiers shown inEmbodiments 1 to 5 in multiple stages.

[0208] Furthermore, the power amplifiers of Embodiments 1 to 5 ormultistage power amplifiers using the above amplifiers are arranged onthe same semiconductor substrate, so that the circuit can be reduced insize.

[0209] Moreover, some are arranged on the same semiconductor substrateand the other parts are arranged on a semiconductor substrate made ofdifferent materials in a different process, so that each excellentcharacteristic can be shared.

[0210] A portable radio of FIG. 6 is configured using the poweramplifiers of Embodiments 1 to 5, so that it is possible to achieve acommunication apparatus such as a portable radio, which can be used atleast at two frequencies with a small size and high efficiency.

[0211] Besides, in the above embodiments, the input terminals 101, 201,and 501, the first switches 103, 203, and 503, the second switches 105,205, and 505, and the third switches 107, 207, and 507 correspond tobranch output means of the present invention. Further, the firstswitches 103, 203, and 503 and the second switches 105, 205, and 505correspond to an amplifying means input switch of the present invention,the third switches 107, 207, and 507 correspond to a bypass input switchof the present invention, and the transmission line 108 corresponds tobypass means of the present invention. Moreover, the input-side DC biassupply circuits 104 c, 204 c, 106 c, 206 c, and 504 c and theoutput-side DC bias supply circuits 104 d, 106 d, 204 d, and 206 dcorrespond to a DC bias supply circuit of the present invention.Additionally, the synchronizing circuits 110, 210, and 510 correspond toa synthesis output unit of the present invention. Further, the fourthswitches 109 and 509 correspond to a transmission line output switch ofthe present invention. Besides, the fourth switch 209 is included ingrounding means of the present invention. Moreover, the input-sidematching circuits 104 a, 204 a, 504 a, 106 a, 206 a, and 506 acorrespond to a first matching circuit of the present invention, and theoutput-side matching circuits 104 b, 204 b, 504 b, 106 b, 206 b, and 506b correspond to a second matching circuit of the present invention.Additionally, the control circuits 113, 213, and 513 correspond tocontrol means of the present invention. Moreover, the first biastransmission line 512 a corresponds to a highest-frequency biastransmission line of the present invention, and the first biastransmission line 512 a and the second bias transmission line 512 dcorrespond to a transmission line group of the present invention.

[0212] Further, in Embodiment 2, the first transmission line 230 and thesecond transmission line 231 correspond to a bypass transmission line ofthe second invention, the fourth switch 209 is included in firstgrounding means of the second invention, and the fifth switch 209 isincluded in second grounding means of the second invention.

INDUSTRIAL APPLICATION

[0213] As is evident from the above description, according to thepresent invention, it is possible to achieve miniaturization and higherefficiency at low output for a power amplifier comprising a plurality ofamplifying means which amplify signals of different frequency bands.

1. A power amplifier, comprising: branch output means having an inputterminal and a plurality of output terminals, a plurality of amplifyingmeans which are connected to some of the output terminals of the branchoutput means and are operated at different signal frequencies from eachother, bypass means connected to the other output terminals of thebranch output means, a synthesis output unit which receives outputs ofthe plurality of amplifying means and an output from the bypass means asinputs and has an output terminal connected to an outside, switch meansof switching presence and absence of conduction of the bypass means, andcontrol means of controlling conduction of the branch output means,conduction and an amplifying operation of the plurality of amplifyingmeans, and conduction of the switch means, wherein according to thesignal frequency and necessary output power, the control means performscontrol so that an input to the branch output means is amplified andoutputted to the synthesis output unit via any one of the plurality ofamplifying means or the input is outputted to the synthesis output unitvia the bypass means without amplification.
 2. A power amplifier,comprising: branch output means having an input terminal and a pluralityof output terminals, a plurality of amplifying means which are connectedto some of outputs of the branch output means and are operated atdifferent signal frequencies from each other, a bypass transmission linegroup which is connected to the other output terminals of the branchoutput means and has a plurality of bypass transmission lines connectedin series with each other, a synthesis output unit connected to eachoutput of the plurality of amplifying means and an output from thetransmission line group, first grounding means which is provided on afirst node of the transmission line group and the branch output meansand permits control of conduction, a plurality of second grounding meanswhich are provided on second nodes between the bypass transmission linesof the transmission line group and permit control of conduction, andcontrol means of controlling conduction of the branch output means,conduction and an amplifying operation of the plurality of amplifyingmeans, conduction of the first grounding means, and conduction of thesecond grounding means, wherein taken from the synthesis output unit, apartial length from the transmission line group to each of the secondnodes and an overall length of the transmission line group correspond toeach of the signal frequencies of the plurality of amplifying means, thepartial lengths starting with the shortest one sequentially correspondto the signal frequencies of the plurality of amplifying means, startingfrom the highest frequency to the lowest frequency, the overall lengthcorresponds to the lowest signal frequency of the plurality ofamplifying means, and according to the signal frequency and necessaryoutput power, the control means performs control so that an input to thebranch output means is amplified and outputted to the synthesis outputunit via any one of the plurality of amplifying means or the input isoutputted to the synthesis output unit via the transmission line groupwithout amplification.
 3. A power amplifier, comprising: branch outputmeans having an input terminal and a plurality of output terminals, aplurality of amplifying means which are connected to some of outputs ofthe branch output means and are operated at different signal frequenciesfrom each other, a transmission line connected to the other outputs ofthe branch output means, a synthesis output unit connected to eachoutput of the plurality of amplifying means and an output from thetransmission line, grounding means which is provided on a side of thebranch output means of the transmission line and permits control ofconduction, and control means of controlling conduction of the branchoutput means, conduction and an amplifying operation of the plurality ofamplifying means, and conduction of the grounding means, wherein thesignal frequencies are different from one another by even number times,and according to the signal frequency and necessary output power, thecontrol means performs control so that an input to the branch outputmeans is amplified and outputted to the synthesis output unit via anyone of the plurality of amplifying means or the input is outputted tothe synthesis output unit via the transmission line withoutamplification.
 4. The power amplifier according to any one of claims 1to 3, wherein the amplifying means comprises: a first matching circuitprovided on a side of the branch input means, a second matching circuitprovided on a side of the synthesis output unit, a transistor providedbetween the first matching circuit and the second matching circuit, anda DC bias supply circuit provided between the first matching circuit andthe transistor and/or between the second matching circuit and thetransistor; and at least one of the first matching circuit and thesecond matching circuit has variable impedance.
 5. The power amplifieraccording to claim 4, wherein the control means changes impedance of oneor both of the first matching circuit and the second matching circuitaccording to output of any one of the plurality of operated amplifyingmeans, the matching circuits being held by the operated amplifyingmeans.
 6. The power amplifier according to claim 4, wherein the firstmatching circuit and/or the second matching circuit comprises: an inputterminal connected to the branch input means or an output side of thetransistor, an output terminal connected to an input side of thetransistor or the synthesis output unit, at least one series matchingcircuit element connected between the input terminal and the outputterminal, at least one switch which is connected between the inputterminal and the series matching circuit element, between the two seriesmatching circuit elements, or between the series matching circuitelement and the output terminal, and is controlled to as to be turned onand off by the control means, and a parallel matching circuit elementconnected to the other end of the switch.
 7. The power amplifieraccording to any one of claims 1 to 3, wherein the branch input meanscomprises: an amplifying means input switch for conduction with each ofthe plurality of amplifying means, and a bypass input switch forconduction with one of the bypass means, the transmission line, and thetransmission line group; and the amplifying means input switch operatesas a distortion pre-compensating circuit.
 8. The power amplifieraccording to claim 7, wherein the amplifying means input switch has adiode controlled so as to be turned on and off by input-side DC bias tothe amplifying means.
 9. The power amplifier according to claim 4,further comprising a DC bias supply circuit for multi frequenciesconnected to a node between the output synthesis unit and the outputterminal, wherein the DC bias supply circuit for multi frequenciesoperates according to the signal frequency corresponding to theoperating amplifying means of the plurality of amplifying means.
 10. Thepower amplifier according to claim 9, wherein the DC bias supply circuitfor multi frequencies comprises: a transmission line group having aplurality of bias transmission lines which correspond to signalfrequencies corresponding to the plurality of amplifying means and areconnected in series with each other, a first bypass capacitor which isconnected to one end of a highest-frequency bias transmission linecorresponding to the highest signal frequency, which is provided on oneend of the transmission line group and has the other end connected tothe node, a first sub switch which is connected in series with the firstbypass capacitor and is controlled so as to be turned on and off by thecontrol means, at least one second bypass capacitor connected betweenthe plurality of bias transmission lines of the transmission line group,a second sub switch connected in series with the second bypasscapacitor, and a bias terminal which is provided on the other end of thetransmission line group, is connected to a side not being connected tothe other bias transmission lines, and is fed with DC bias supplied fromthe control means; and the other end of the highest-frequency biastransmission line is grounded via the first bypass capacitor and thefirst sub switch, grounding is made between the plurality of biastransmission lines of the transmission line group other than the otherend of the highest-frequency bias transmission line via the secondbypass capacitor and the second sub switch, the first bypass capacitoris short-circuited at the highest signal frequency of the signalfrequencies, and the second bypass capacitor is short-circuited at thesignal frequency associated with a sum of lengths of transmission linesfrom the connecting position to the node.
 11. A power amplifier having amultistage constitution, wherein the power amplifier described in anyone of claims 1 to 10 is combined and used as an amplifier of at leastone stage or more.
 12. A power amplifier, wherein all or some parts ofthe power amplifier described in any one of claims 1 to 10 areconfigured on the same semiconductor substrate.
 13. A power amplifier,wherein all or some parts of the power amplifier described in any one ofclaims 1 to 10 are configured on a plurality of different semiconductorsubstrates from each other.
 14. A communication apparatus, comprising: asignal processing circuit, a transmitting circuit which transmits asignal from the signal processing circuit and has a power amplifier, anantenna which transmits an output of the transmitting circuit andreceives a reception signal, and a receiving circuit of processing thereception signal, wherein the power amplifier is the power amplifierdescribed in any one of claims 1 to 13.